The invention relates generally to integrated circuit fabrication and, in particular, to methods for fabricating wiring structures during back-end-of-line (BEOL) processing of semiconductor chips, BEOL wiring structures, and design structures for a BEOL wiring structure.
A BEOL wiring structure is used to route signals to and from the active devices of an integrated circuit and to provide power to and among the various circuit functions on a chip. The BEOL wiring structure may include wiring embedded in a stack of dielectric layers to create a stack of metallization levels defining an interconnection network for the signals and power. The BEOL wiring structure may be fabricated using damascene processes in which the metallization levels are individually formed.
On-chip inductors are passive devices commonly utilized in monolithic integrated circuits designed to operate at high frequencies, such as those found in wireless communication devices. In particular, on-chip inductors may be utilized in radiofrequency integrated circuits (RFICs), which are found in applications such as Phase-Locked Loop (PLL) transmitters, voltage controlled oscillators (VCOs), impedance matching networks, filters, etc.
On-chip inductors may be integrated into one or more of the metallization levels of the BEOL wiring structure. On-chip inductors may be formed with standard semiconductor processing steps used to form BEOL wiring structures and without the necessity of introducing additional processing steps or additional masks. In particular, an on-chip inductor may be comprised of wires disposed within one or more metallization levels of the BEOL wiring structure.
Improved methods for fabricating a BEOL wiring structure, as well as improved BEOL wiring structures and improved design structures for a BEOL wiring structure, are needed.